Most SRAMs today utilize a six transistor (6T) cell as shown in FIG. 1 of the accompanying drawings. Such designs can suffer from:
1. High static power consumption.
2. In modem manufacturing processes transistor performance variability is leading to memory operation limitations such as memory cell stability and manufacturing yield issues
3. Existing proposed solutions result in the use of greater silicon area.
In FIG. 1, a wordline wl selects a row of such cells in an array. Bitlines bl_t/c of the cells are connected orthogonally in columns. Usually the bitlines are precharged to the supply voltage Vdd ready for a read or write operation.
In a read operation, the cell selected by having its wordline raised to Vdd will pull either the true (bl_t) or complement (bl_c) bitline low creating a differential voltage on the bitline pair. This differential voltage can be sensed by an amplifier (the senseamp) connected to the column which recovers the read data to full rail (vdd and gnd). Often column multiplexing is employed to selected one of a set of columns to connect to the senseamp.
To write to a cell, the wordline is selected and full rail write data is driven onto the bitlines by the write drivers: to write 1 bl_t is driven to Vdd and bl_c to gnd and visa versa to write 0.
The standard 6T cell design has been used for many years, but there are some issues affecting the performance of this cell in modem semiconductor processes.
One such problem is that the wordline access devices A_t/c leak. This is a problem in itself because it increases the current consumption in standby mode, where the SRAM is powered up but is not being accessed. It is also potentially a problem in the operation of the SRAM. In a pathological case all cells on a bitline may store 0 except the one you want to read which stores 1. Reading that cell discharges bl_c, but all the other cells are seeing full Vdd across the access device A_t because the bitline is precharged and data_t=gnd. Thus, there is a leakage path through all the A_t devices in the other cells which can add up to reduce or even over-take the differential building on the other, actively read, bitline. This slows, or even corrupts the data being read. To circumvent this problem the number of cells per bitline column is reduced and the resulting sub-bitlines are connected hierarchically. The extra peripheral circuitry involved increases area, power consumption and complexity.
The leakage through the access devices is exacerbated by reverse narrow width effect [3]. This physical effect on small nmos devices causes their Vtn to be lower than normally sized devices. Lower Vtn means higher leakage.
Another problem is in the cell design itself. The cell stability, the ability of the cell to store and retain data safely, is affected by the relative sizes of the drive transistors (D_t/c) and access transistors (A_t/c). The beta ratio, the ratio of the strengths of these transistors (the drive beta divided by the access beta), must reach a certain level for the cell to be stable. Traditionally, the beta ratio should be a minimum of 1.5 in the 6T cell above.
The pmos transistors P_t/c also have an effect. Stronger pmos devices give a more stable cell, but if they are too strong the cell is more difficult to write to: the bitline write driver has to drive a long highly capacitive bitline, then through the weak access devices A_t/c and finally over-drive the pmos device. If the pmos are too strong, writes may fail.
Cell stability is often quantified by a metric known as static noise margin (SNM). The SNM of a particular cell design can be simulated: the higher the SNM, the more stable and more immune to noise the cell is.
The worst case operating point for stability of the traditional 6T cell is when wordline=Vdd and both bitlines=Vdd. This occurs during read or write when a column on a selected row is not being read or written but the bitlines are held precharged at Vdd. These conditions are collectively known has half-select. The SNM during half-select is usually much lower than during unselected states (i.e. when the wordline is gnd). Worst case SNM also occurs at the very start of a read operation, before the read has a chance to build differential on the bitline.
SNM also reduces with Vdd: the lower the Vdd, the lower the SNM. Manufacturing process variations across a given SRAM array cause a distribution of SNM: inevitably some cells in the array have lower SNM. On some cells, the SNM is so bad that the cell fails to operate. These so called soft fails are therefore proportional to Vdd (as opposed to hard fails which fail at all Vdd values and are related to physical defects with the cell). The stability of the cell during half-select limits the minimum voltage at which the SRAM can operate, because below that voltage soft-fails cause unacceptable yield loss.
Soft-fails are increasing as process geometries shrink causing higher variability in transistor performance within a chip. Pilo et al. [2] estimate that soft fails overtake hard fails between the 90 nm and 65 nm process generations. This is due to the transistor dimensions (oxide thicknesses, channel lengths etc.) approaching atomic levels. Any variations intrinsic to the manufacturing process will have a proportionally bigger effect on the smallest transistors on the chip. SRAMs are being particularly badly hit by the on chip variations because they contain these very small transistors, notably the access and P-load devices.